The design optimization and implementation of broadband high-frequency fishing sonar based on FPGA

An field programmable gate array (FPGA)-based method for optimizing the receiver is proposed to address the problems of excessive resource consumption and high hardware cost of wideband high-frequency sonar. The method starts by pulse-compressing the analog-to-digital converted signal and windowing the filter coefficients, followed by down-mixing the signal and then simple modulus solving for envelope processing to achieve the reduction in resource consumption. Simulation results show that the signal processing method of the optimized receiver reduces the block random access memory (BRAM) resource consumption by about 86% and the Multiplier (MULT) resource consumption by about 80% compared to the pre-optimized BRAM, without any loss in performance. The results of the anechoic pool test show that this method can achieve a distance resolution of 3 cm at a range of 2 m. The sonar realized by this research method can be applied to early warning of disaster-causing organisms in China's nuclear power generation, detection of resources in shallow waters, and bio-monitoring of aquaculture nets, etc., which is of great application value.